1. Field of the Invention
This invention relates to electronic circuits, and in particular to a field effect transistor circuit used as a load circuit, for example, in inverters, logic gates, and static metal oxide semiconductor random access memories.
2. Description of the Prior Art
In many semiconductor applications requiring load elements, for example, inverters, logic gates and static memory systems, a termination circuit includes a single depletion mode field effect transistor (FET) having a drain connected to a voltage supply bus, and having gate and source connected together and to a node to be pulled-up. A depletion mode FET connected in this manner is always conducting, but current limiting. Depletion mode FET's are superior load elements when compared to enhancement mode FET's and resistors, because of the constant current source characteristics of the depletion mode. A pure depletion load provides more charging current for the same short circuit current. This allows faster operation at the same power levels.
Quite often, however, the voltage to which a node is to be pulled is an intermediate high voltage, for example, one enhancement threshold voltage below the high voltage. As a result an enhancement mode FET is often placed between the high pull-up voltage and the depletion mode FET. The gate of the enhancement mode FET is tied to the high pull-up voltage and the gate of the depletion mode FET is tied to its source which is the node to be pulled-up. The drain of the depletion mode FET is connected to the source of the enhancement mode FET. Such a circuit configuration offers an intermediate high potential and behaves as a constant current source load. Unfortunately, because some of the voltage drop occurs across the enhancement mode FET, a pure depletion load line characteristic is not achievable unless the enhancement mode transistor is infinitely larger than the depletion mode transistor. Because this solution is impractical, such a circuit configuration typically has a load line characteristic somewhere between enhancement and depletion type transistors. A circuit of this type is described in more detail in U.S. Pat. No. 4,195,356 entitled "Sense Line Termination Circuit for Semiconductor Memory Systems."